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1. general description the px1011b is a high-performance, low-po wer, single-lane pci express electrical physical layer (phy) that handles the low level pci express protocol and signaling. the px1011b pci express phy is compliant to the pci express base specification, rev. 1.0a , and rev. 1.1 . the px1011b includes features such as clock and data recovery (cdr), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection, and pr ovides superior performance to the media access control (mac) layer devices. the px1011b is a 2.5 gbit/s pci express phy with 8-bit data pxpi pe interface. its pxpipe interface is a supers et of the phy interface fo r the pci express (pipe) specification, enhanced and adapted for off-ch ip applications with the introduction of a source synchronous clock for transmit and receive data. the 8-bit data interface operates at 250 mhz with sstl_2 signaling. the sst l_2 signaling is compatible with the i/o interfaces available in fpga products. the px1011b pci express phy supports ad vanced power management functions. the px1011bi is for the industrial temperature range ( ? 40 ? c to +85 ? c). automotive aec-q100 compliant vers ion px1011b-el1/q900 is available. 2. features and benefits 2.1 pci express interface ? compliant to pci express base specification 1.1 ? single pci express 2.5 gbit/s lane ? data and clock recovery from serial stream ? serializer and de-serializer (serdes) ? receiver detection ? 8b/10b coding and decoding, elastic buffer and word alignment ? supports loopback ? supports direct disparity control for use in transmitting compliance pattern ? supports lane polarity inversion ? low jitter and bit error rate (ber) 2.2 phy/mac interface ? based on intel phy interface for pci express architecture v1.0 (pipe) ? adapted for off-chip with additional synchronous clock signals (pxpipe) ? 8-bit parallel data interface for transmit and receive at 250 mhz ? 2.5 v sstl_2 class i signaling px1011b pci express stand-alone x1 phy rev. 6 ? 27 june 2011 product data sheet
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 2 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 2.3 jtag interface ? jtag (ieee 1149.1) boundary scan interface ? built-in self test (bist) controller tests serdes and i/o blocks at speed ? 3.3 v cmos signaling 2.4 power management ? dissipates < 300 mw in l0 normal mode ? support power management of l0, l0s and l1 2.5 clock ? 100 mhz external reference clock with ? 300 ppm tolerance ? supports spread spectrum clock to reduce emi ? on-chip reference clock termination 2.6 miscellaneous ? lfbga81 leaded or lead-free packages ? operating ambient temperature ? commercial: 0 ? c to +70 ? c ? industrial: ?40 ? c to +85 ? c ? esd protection voltage for human body model (hbm): 2000 v 3. quick reference data table 1. quick reference data symbol parameter conditions min typ max unit v ddd1 digital supply voltage 1 for jtag i/o 3.0 3.3 3.6 v v ddd2 digital supply voltage 2 for sstl_2 i/o 2.3 2.5 2.7 v v ddd3 digital supply voltage 3 for core 1.15 1.2 1.3 v v dd supply voltage for high-speed serial i/o and pvt 1.15 1.2 1.3 v v dda1 analog supply voltage 1 for serializer 1.15 1.2 1.3 v v dda2 analog supply voltage 2 for serializer 3.0 3.3 3.6 v f clk(ref) reference clock frequency 99.97 100 100.03 mhz t amb ambient temperature operating commercial 0 - +70 ?c industrial ? 40 - +85 ?c
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 3 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 4. ordering information [1] px1011b-el1/q900 is aec-q100 compliant. contact i2c.support@nxp.com for ppap. 5. marking [1] industrial temperature range. table 2. ordering information type number solder process package name description version px1011b-el1/g pb-free (snagcu solder ball compound) lfbga81 plastic low profile fine-pitch ball grid array package; 81 balls; body 9 ? 9 ? 1.05 mm sot643-1 px1011b-el1/n snpb solder ball compound lfbga81 plastic low profile fine-pitch ball grid array package; 81 balls; body 9 ? 9 ? 1.05 mm sot643-1 PX1011BI-EL1/g pb-free (snagcu solder ball compound) lfbga81 plastic low profile fine-pitch ball grid array package; 81 balls; body 9 ? 9 ? 1.05 mm sot643-1 px1011b-el1/q900 [1] pb-free (snagcu solder ball compound) lfbga81 plastic low profile fine-pitch ball grid array package; 81 balls; body 9 ? 9 ? 1.05 mm sot643-1 table 3. leaded package marking line marking description a px1011b-el1/n full basic type number b xxxxxxx diffusion lot number c 2pnyyww manufacturing code: 2 = diffusion site p = assembly site n = leaded yy = year code ww = week code table 4. lead-free package marking line marking description a px1011b-el1/g PX1011BI-EL1/g [1] px1011b-el1/q [1] full basic type number b xxxxxxx diffusion lot number c 2pgyyww manufacturing code: 2 = diffusion site p = assembly site g = lead-free yy = year code ww = week code
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 4 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 6. block diagram fig 1. block diagram 8 10 002aac211 ln_txdata0 tx i/o refclk i/o refclk_p register pci express phy pci express mac ln_txdata1 reset_n rxdata [ 7:0 ] txdata [ 7:0 ] txclk rxclk 8b/10b encode 10b/8b decode refclk_n tx_p tx_n rx i/o rx_p bit stream at 2.5 gbit/s rx_n elastic buffer k28.5 detection clock recovery circuit pll clk generator 250 mhz clock parallel to serial serial to parallel data recovery circuit
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 5 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 7. pinning information 7.1 pinning fig 2. pin configuration for lfbga81 002aad017 transparent top view j h g f e d b c a 246 9 8 1357 ball a1 index area px1011b-el1/g px1011b-el1/n PX1011BI-EL1/g px1011b-el1/q900 transparent top view. fig 3. ball mapping 1 a 002aad018 v ss rxidle rxdata6 rxdata4 rxdata3 rxdata1 rxdatak rxclk rxstatus0 23456789 b refclk_p v ss rxdata7 rxdata5 v ss rxdata2 rxdata0 v ss rxstatus1 c refclk_n v ss v ddd2 v ss v ddd2 v ss v ddd2 rxvalid rxstatus2 d v ss v ss v dd v dda2 v dda1 pvt v ss phystatus txdata0 e rx_p v ss v ddd1 tms v ddd1 v ddd3 v ddd2 v ss txdata1 f rx_n v ss tck trst_n v ddd3 v ddd3 v ss txdata3 txdata2 g v ss v ss tdi v ss v ddd2 v ss v ddd2 txdata5 txdata4 h tx_p v ss tdo txidle v ss pwrdwn0 rxdet_ loopb v ss txdata6 j tx_n vrefs reset_n rxpol txcomp pwrdwn1 txdatak txclk txdata7
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 6 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 7.2 pin description the phy input and output pins are described in ta b l e 5 to ta b l e 1 2 . note that input and output is defined from the perspective of the phy. thus a signal on a pin described as an output is driven by the phy and a signal on a pin described as an input is received by the phy. a basic description of each pin is provided. table 5. pci express serial data lines symbol pin type signaling description rx_p e1 input pcie i/o differential input receive pair with 50 ? on-chip termination rx_n f1 input pcie i/o tx_p h1 output pcie i/o differential output transmit pair with 50 ? on-chip termination tx_n j1 output pcie i/o table 6. pxpipe interface tr ansmit data signals symbol pin type signaling description txdata[7:0] j9, h9, g8, g9, f8, f9, e9, d9 input sstl_2 8-bit transmit data input from the mac to the phy txdatak j7 input sstl_2 selection input for the symbols of transmit data; low = data byte; high = control byte table 7. pxpipe interface receive data signals symbol pin type signaling description rxdata[7:0] b3, a3, b4, a4, a5, b6, a6, b7 output sstl_2 8-bit receive dat a output from the phy to the mac rxdatak a7 output sstl_2 selection output for the symbols of receive data; low = data byte; high = control byte table 8. pxpipe interface command signals symbol pin type signaling description rxdet_ loopb h7 input sstl_2 used to tell the phy to begin a receiver detection operation or to begin loopback; low = reset state txidle h4 input sstl_2 forces tx output to electrical idle. txidle should be asserted while in power states p0s and p1. txcomp j5 input sstl_2 used when transmitting the compliance pattern; high-level sets the running disparity to negative rxpol j4 input sstl_2 signals the phy to perform a polarity inversion on the receive data; low = phy does no polarity inversion; high = phy does polarity inversion reset_n j3 input sstl_2 phy reset input; active low pwrdwn0 h6 input sstl_2 transceiver power-up and power-down inputs (see table 13 ); 0x2 = reset state pwrdwn1 j6 input sstl_2
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 7 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy table 9. pxpipe interfa ce status signals symbol pin type signaling description rxvalid c8 output sstl_2 indicates symbol lock and valid data on rx_data and rx_datak phystatus d8 output sstl_2 used to communicate completion of several phy functions including power management state transitions and receiver detection rxidle a2 output sstl_2 indicates receiver detection of an electrical idle; this is an asynchronous signal rxstatus0 a9 output sstl_2 encodes receiver status and error codes for the received data stream and receiver detection (see ta b l e 1 5 ) rxstatus1 b9 output sstl_2 rxstatus2 c9 output sstl_2 table 10. clock and reference signals symbol pin type signaling description txclk j8 input sstl_2 source synchronous 250 mhz transmit clock input from mac. all inpu t data and signals to the phy are synchronized to this clock. rxclk a8 output sstl_2 source synchronous 250 mhz clock output for received data and status signals bound for the mac. refclk_p b1 input pcie i/o 100 mhz reference clock input. this is the spread spectrum source clock for pci express. differential pair input with 50 ? on-chip termination. refclk_n c1 input pcie i/o pvt d6 - analog i/o input or output to create a compensation signal internally that will adjust the i/o pads characteristics as pvt drifts. connect to v dd through a 49.9 ? resistor. vrefs j2 input reference voltage input for sstl_2 class i signaling. connect to 1.25 v. table 11. 3.3 v jtag signals symbol pin type signaling description tms e4 input 3.3 v cmos test mode select input trst_n f4 input 3.3 v cmos test reset input for the jtag interface; active low tck f3 input 3.3 v cmos test clock input for the jtag interface tdi g3 input 3.3 v cmos test data input tdo h3 output 3.3 v cmos test data output
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 8 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 8. functional description the main function of the phy is to convert digital data into electrical signals and vice versa. the pci express phy handles the low level pci express protocol and signaling. the px1011b pci express phy consists of the physical coding sub-layer (pcs), a serializer and de-serializer (serdes) and a set of i/os (pads). the pci express phy handles the low level pci express protocol and signaling. this includes features such as clock and data recovery (cdr), data serialization and de-serialization, 8b/10b encoding, analog buffers, elastic buffer and receiver detection. the pxpipe interface between the mac and px1011b is a su perset of the phy interface for the pci express (pipe) specification. the following feature have been added: ? source synchronous clocks for rx and tx data to simplify timing closure. the 8-bit data width pxpipe interface o perates at 250 mhz with sstl_2 class i signaling. px1011b does not integrate sstl_2 termination resistors inside the ic. the pci express link consists of a differential i nput pair and a differential output pair. the data rate of these signals is 2.5 gbit/s. 8.1 receiving data incoming data enters the chip at the rx inte rface. the receiver converts these signals from small amplitude differential signals into rail-to-rail digital signal s. the carrier detect circuit detects whether data is present on the line and passes this information through to the serdes and pcs. if a valid stream of data is present the clock and data recovery unit (cdr) first recovers the clock from the data and then uses this clock for re-timing the data (i.e., recovering the data). table 12. pci express phy power supplies symbol pin type signaling description v dda1 d5 power 1.2 v analog power supply for serializer and de-serializer v dda2 d4 power 3.3 v analog power supply for serializer and de-serializer v ddd1 e3, e5 power 3.3 v power supply for jtag i/o v ddd2 c3, c5, c7, e7, g5, g7 power 2.5 v power supply for sstl_2 i/o v ddd3 e6, f5, f6 power 1.2 v power supply for core v dd d3 power 1.2 v power supply for high-speed serial pci express i/o pads and pvt v ss a1, b2, b5, b8, c2, c4, c6, d1, d2, d7, e2, e8, f2, f7, g1, g2, g4, g6, h2, h5, h8 ground ground
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 9 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy the de-serializer or serial-to-parallel converte r (s2p) de-serializes this data into 10-bits parallel data. since the s2p has no knowledg e about the data, the word a lignment is still random. this is fixed in the digital domain by the pcs bloc k. it first detects a 10-bit comma character (k28.5) from the random data stream and aligns the bits. then it converts the 10-bit raw data into 8-bit words using 8b/10b decoding. an elastic buffer and fifo brings the resulting data to the right clock domain, which is the rx source synchronous clock domain. 8.2 transmitting data when the phy transmits, it rece ives 8-bit data from the mac. this data is encoded using an 8b/10b encoding algorithm. the 2 bits overhead of the 8b/10b encoding ensures the serial data will be dc-balanced and has a sufficie nt 0-to-1 and 1-to-0 transition density for clock recovery at the receiver side. the serializer or parallel-to-serial converter (p2s) serializes the 10 bits data into serial data streams. these data streams are latched into the transmitter, where they are converted into small amplitude differential signals. the transmitter has built-in de-emphasis for a larger eye opening at the receiver side. the pll has a sufficiently high bandwidth to handle a 100 mhz reference clock with a 30 khz to 33 khz spread spectrum. 8.3 clocking there are three clock signals used by the px1011b: ? refclk is a 100 mhz external reference clock that the phy uses to generate the 250 mhz data clock and the internal bi t rate clock. this clock may have 30 khz to 33 khz spread spectrum modulation. ? txclk is a reference clock that the phy uses to clock the txdata and command. this source synchronous clock is provided by the mac. the phy expects that the rising edge of txclk is centered to the data. the txclk has to be synchronous with rxclk. ? rxclk is a source synchronous clock provided by the phy. the rxdata and status signals are synchronous to this clock. the phy aligns the rising edge of rxclk to the center of the data. rxclk may be used by the mac to clock its internal logic. 8.4 reset the phy must be held in reset until power and refclk are stable. it takes the phy 64 ? s maximum to stabilize its internal clocks. rxclk frequency is the same as refclk frequency, 100 mhz, during this time. the phy de-asserts phystatus when internal clocks are stable. the pipe specification recommends that while reset_n is assert ed, the mac should have rxdet_loopb de-asserted, txidle asserted, txcomp de-asserted, rxpol de-asserted and power state p1. the mac can also assert a reset if it receives a physical layer reset packet.
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 10 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 8.5 power management the power management signals allow the phy to manage power consumption. the phy meets all timing constraints provided in the pci express base specification regarding clock recovery and link training for the various power states. four power states are defined: p0, p0s, p1 and p2. p0 state is the normal operational state for the phy. when directed from p0 to a lower power state, the phy can immediately take whatever power saving measures are appropriate. in states p0, p0s and p1, the phy keeps internal clocks operational. for all state transitions between these three states, the ph y indicates successful transition into the designated power state by a single cycle assertion of phystatus. for all power state transitions, the mac must not begin any oper ational sequences or further power state transitions until the phy has indi cated that the initial state transition is completed. txidle should be asserted while in power states p0s and p1. ? p0 state: all internal clocks in the phy are operational. p0 is the only state where the phy transmits and receives pci express sig naling. p0 is the appropriate phy power management state for most states in the link training and status state machine (ltssm). exceptions are listed for each lower power phy state (p0s, p1 and p2). ? p0s state : the mac will move the phy to this st ate only when the transmit channel is idle. while the phy is in either p0 or p0s power states, if the receiver is detecting an electrical idle, the receiver portion of the phy can take appropriate power saving measures. note that the phy is capable of obtaining bit an d symbol lock within the phy-specified time (n_fts with or without common clock) upon resumption of signaling on the receive channel. this requirement only applies if the receiver had previously been bit and symbol locked while in p0 or p0s states. ? p1 state : selected internal clo cks in the phy are turned off. the mac will move the phy to this state only when both transmit and receive channels are idle. the phy indicates a successful entry into p1 (by asserting phystatus). p1 should be used for the disabled state, all detect states, and l1.idle state of the link training and status state machine (ltssm). ? p2 state : phy will enter p1 instead. fig 4. reset 002aac172 rxclk reset_n phystatus 100 mhz 250 mhz
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 11 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy [1] txidle = 0 [2] txidle = 1 8.6 receiver detect when the phy is in the p1 state, it can be instructed to perform a receiver detection operation to determine if there is a receiver at the other end of the lin k. basic operation of receiver detection is that the mac requests th e phy to do a receiver detect sequence by asserting rxdet_loopb. when the phy has completed the receiver detect sequence, it drives the rxstatus signals to the value of 011b if a receiver is present, and to 000b if there is no receiver. then the phy will assert phystatus to indicate the completion of receiver detect operation. the mac uses th e rising edge of phystatus to sample the rxstatus signals and then de-asserts rxdet_loopb. a few cycles after the rxdet_loopb de-asserts, the phystatus is also de-asserted. 8.7 loopback the phy supports an internal loopback from the pci express receiver to the transmitter with the following characteristics. the phy retransmits each 10-bit data and control symbol exactly as received, without applying scrambling or descrambling or disparity corrections, with the following rules: ? if a received 10-bit symbol is determined to be an invalid 10-bit code (i.e., no legal translation to a cont rol or data value possible), the phy still retransmits the symbol exactly as it was received. ? if a skp ordered set retransm ission requires adding a skp symbol to accommodate timing tolerance correcti on, any disparity can be chosen for the skp symbol. table 13. summary of power management state pwrdwn[1:0] power management state transmitter receiver tx pll rxclk rx pll/cdr 00b p0, normal operation on [1] on on on on 01b p0s, power saving state idle [2] idle on on on 10b p1, lower power state idle [2] idle on on off 11b illegal, phy will enter p1 - - - - - fig 5. receiver detect - receiver present 002aac173 rxclk 000b 10b 011b 000b phystatus rxstatus2, rxstatus1, rxstatus0 txclk rxdet_loopb pwrdwn1, pwrdwn0
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 12 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy ? the phy continues to provide the received data on the pxpipe interface, behaving exactly like normal data reception. ? the phy transitions from norm al transmission of data from the pxpipe interface to looping back the received data at a symbol boundary. the phy begins to loopback data when the mac asserts rxdet_loopb while doing normal data transmis sion. the phy stops transmitting data from the pxpipe interface, and begins to loopback received symbols. while doing loopback, the phy continues to present received data on the pxpipe interface. the phy stops looping back received data when the mac de-asserts rxdet_loopb. transmission of data on the parallel interface begins immediately. the timing diagram of figure 6 shows example timing for beginning loopback. in this example, the receiver is receiving a repeat ing stream of bytes, rx-a through rx-z. similarly, the mac is causing the phy to tr ansmit a repeating st ream of bytes tx-a through tx-z. when the mac asserts rxdet_loopb to the phy, the phy begins to loopback the received data to the differential tx_p and tx_n lines. the timing diagram of figure 7 shows an example of switching from loopback mode to normal mode. as soon as the mac detects an electrical idle ordered-set, the mac de-asserts rxdet_loopb, asserts txidle and changes the powerdown signals to state p1. fig 6. loopback start rxdet_loopb 002aac174 rxclk txclk rx-c rx-d rx-e rx-f rx-g tx-m tx-n tx-o tx-p tx-q tx-m tx-n rx-e tx_p, tx_n rxdata[7:0] txdata[7:0]
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 13 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 8.8 electrical idle the pci express base specification requires that devices send an electrical idle ordered-set before tx goes to the electrical idle state. the timing diagram of figure 8 shows an example of timing for entering electrical idle. fig 7. loopback end rxdet_loopb 001aac785 rxclk rxdata[7:0] txidle tx_p, tx_n txclk com idl junk looped back rx data junk includes electrical idle ordered set fig 8. electrical idle txidle 002aac175 txclk txdata[7:0] txdatak sczero com idl active (ends with electrical idle ordered-set) tx_p, tx_n
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 14 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy ta b l e 1 4 summarizes the function of some pxpipe control signals. 8.9 clock tolerance compensation the phy receiver contains an elastic buffer used to compensate for differences in frequencies between bit rates at the two ends of a link. the elastic buffer is capable of holding at least seven symbols to handle worst case differences (600 ppm) in frequency and worst case intervals between skp ordered-sets. the phy is responsible for inserting or removing skp symbols in the received data stream to avoid elastic buffer overflow or underflow. the phy monitors the receive data stream, and when a skip ordered-set is received, the phy can add or remove one skp symbol from each skp orde red-set as appropriate to manage its el astic buffer. whenever a skp symbol is added or removed, the phy will signal this to the mac using t he rxstatus signals. these signals have a non-zero value for one clo ck cycle and indicate whether a skp symbol was added or removed from the received skp ordered-set. rxstatus should be asserted during the clock cycle when the com symbo l of the skp ordered-set is moved across the parallel interface. if the removal of a skp symbol causes no skp symbols to be transferred across the parallel interface, th en rxstatus is asserted at the same time that the com symbol (that was part of the received skip ordered-set) is transmitted across the parallel interface. figure 9 shows a sequence where the phy inserted a skp symbol in the data stream. figure 10 shows a sequence where the phy removed a skp symbol from a skp ordered-set. table 14. control sign als function summary pwrdwn[1:0] rxdet_loopb txidle function description p0: 00b 0 0 normal operation 0 1 transmitter in idle 1 0 loopback mode 1 1 illegal p0s: 01b x 0 illegal 1 transmitter in idle p1: 10b x 0 illegal 0 1 transmitter in idle 1 1 receiver detect fig 9. clock correction - insert a skp 001aac779 rxclk active com skp 000b 001b 000b skp active rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 15 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 8.10 error detection the phy is responsible for detecting receive errors of several types. these errors are signaled to the mac layer using the receiver status signals rxstatus. because of higher level error detection mech anisms (like crc) built into the data link layer of pci express, there is no need to specifically identify symbols with errors. however, timing information about when the error occurred in the data stream is important. when a receive error occurs, the ap propriate error code is asserted for one clock cycle at the point closest to where the error actually occurred. there are four error conditions that can be encoded on the rxstatus signals. if more than one error should happen to occur on a received byte, the errors are signaled with the priority shown below. 1. 8b/10b decode error 2. elastic buffer overflow 3. elastic buffer underflow 4. disparity error fig 10. clock correction - remove a skp 002aac176 rxclk active com skp 000b 010b 000b active rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0 table 15. function table pxpipe status interface signals operating mode output pin rxstatus2 rxstatus1 rxstatus0 received data ok l l l one skp added l l h one skp removed l h l receiver detected l h h 8b/10b decode error h l l elastic buffer overflow h l h elastic buffer underflow h h l receive disparity error h h h
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 16 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 8.10.1 8b/10b decode errors for a detected 8b/10b decode error, the phy places an edb (end bad) symbol in the data stream in place of the bad byte, and encodes rxstatus with a decode error during the clock cycle when the effected byte is tr ansferred across the parallel interface. in figure 11 the receiver is receiving a stream of by tes rx-a through rx-z, and byte rx-c has an 8b/10b decode error. in place of that byte, the phy places an edb on the parallel interface, and sets rxstatus to the 8b/10b decode error code. note that a byte that cannot be decoded may also have bad disp arity, but the 8b/10b error has precedence. 8.10.2 disparity errors for a detected disparity error, the phy asse rts rxstatus with the disparity error code during the clock cycle when the effected byte is transferred across the parallel interface. in figure 12 the receiver detected a disparity error on rx-c data byte, and indicates this with the assertion of rxstatus. 8.10.3 elastic buffer for elastic buffer errors, an underflow is signa led during the clock cycle when the spurious symbol is moved across the parallel interface. the symbol moved across the interface is the edb symbol. in the timing diagram figure 13 , the phy is receiving a repeating set of symbols rx-a through rx-z. the elastic buffer underflow causing the edb symbol to be inserted between the rx-c and rx-d symbol s. the phy drives rxstatus to indicate buffer underflow during the clock cycle when the edb is presented on the parallel interface. fig 11. 8b/10b decode errors 001aac780 rxclk rx-a rx-b edb 000b 100b 000b rx-d rx-e rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0 fig 12. disparity errors 001aac781 rxclk rx-a rx-b rx-c 000b 111b 000b rx-d rx-e rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 17 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy for an elastic buffer overflow, the overflow is signaled during the clock cycle where the dropped symbol would have appeared in the data stream. in the timing diagram of figure 14 , the phy is receiving a repeating set of symbols rx-a through rx-z. the elastic buffer overflows causing the symbol rx-d to be discarded. the phy drives rxstatus to indicate buffer overflow during the clock cycle when rx-d would have appeared on the parallel interface. 8.11 polarity inversion to support lane polarity inversion, the phy inverts received data when rxpol is asserted. the phy begins data inversion within 20 symbols after rxpol is asserted. fig 13. elastic buffer underflow fig 14. elastic buffer overflow 001aac782 rxclk rx-a rx-b rx-c 000b 110b 000b edb rx-d rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0 001aac783 rxclk rx-a rx-b rx-c 000b 101b 000b rx-e rx-f rxvalid rxdata[7:0] rxstatus2, rxstatus1, rxstatus0 fig 15. polarity inversion 001aac786 rxclk d21.5 d21.5 d10.2 d10.2 rxpol rxvalid rxdata[7:0]
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 18 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 8.12 setting negative disparity to set the running disparity to negative, the mac asserts txcomp for one clock cycle that matches with the data that is to be transmitted with negative disparity. 8.13 jtag boundary scan interface joint test action group (jtag) or ieee 1149.1 is a stan dard, specifying how to control and monitor the pins of compliant devices on a printed-circuit board. this standard is commonly known as ?jtag boundary scan?. this standard defines a 5-pin serial protocol for accessing and controlling the signal levels on the pins of a digital circuit, and has some extensions for testing th e internal circuitry on the chip itself, which is beyond the scope of this data sheet. access to the jtag interface is provided to the customer for the sole purpose of using boundary scan for interconnect test verificati on between other complia nt devices that may reside on the board. using jtag for purposes other than boundary scan may produce undesired effects. the jtag interface is a 3.3 v cmos signalin g. jtag trst_n must be asserted low for normal device operation. if jtag is not planned to be used, it is recommended to pull down trst_n to v ss . fig 16. setting negative disparity 002aac177 txclk data k28.5 k28.5 valid data k28.5? k28.5+ k28.5 k28.5 tx_p, tx_n txcomp txdata[7:0] byte transmitted with negative disparity
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 19 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 9. limiting values [1] human body model: ansi/eos/esd-s5.1-1994, standard for esd sensitivity testing, human body model - component level; electrostatic disc harge association, rome, ny, usa. [2] charged device model: ansi/eos/esd-s5.3.1-1999, st andard for esd sensitivity testing, charged device model - component level; electrostatic discharge association, rome, ny, usa. 10. thermal characteristics [1] significant variations can be expected due to system va riables, such as adjacent dev ices, or actual air flow across the package. table 16. limiting values in accordance with the absolute maximum rating system (iec 60134). symbol parameter conditions min max unit v ddd1 digital supply voltage 1 for jtag i/o ? 0.5 +4.6 v v ddd2 digital supply voltage 2 for sstl_2 i/o ? 0.5 +3.75 v v ddd3 digital supply voltage 3 for core ? 0.5 +1.7 v v dd supply voltage for high-speed serial i/o and pvt ? 0.5 +1.7 v v dda1 analog supply voltage 1 for serializer ? 0.5 +1.7 v v dda2 analog supply voltage 2 for serializer ? 0.5 +4.6 v v esd electrostatic discharge voltage hbm [1] - 2000 v cdm [2] -500v t stg storage temperature ? 55 +150 ?c t j junction temperature ? 55 +125 ?c t amb ambient temperature operating commercial 0 +70 ?c industrial ? 40 +85 ?c table 17. thermal characteristics symbol parameter conditions typ unit r th(j-a) thermal resistance from junction to ambient in free air [1] 44 k/w r th(j-c) thermal resistance from junc tion to case in free air [1] 10 k/w
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 20 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 11. characteristics table 18. pci express phy characteristics symbol parameter conditions min typ max unit supplies v ddd1 digital supply voltage 1 for jtag i/o 3.0 3.3 3.6 v v ddd2 digital supply voltage 2 for sstl_2 i/o 2.3 2.5 2.7 v v ddd3 digital supply voltage 3 for core 1.15 1.2 1.3 v v dd supply voltage for high-speed serial i/o and pvt 1.15 1.2 1.3 v v dda1 analog supply voltage 1 for serializer 1.15 1.2 1.3 v v dda2 analog supply voltage 2 for serializer 3.0 3.3 3.6 v i ddd1 digital supply current 1 for jtag i/o 0.1 1 2 ma i ddd2 digital supply current 2 for sstl_2; no load - 24 35 ma i ddd3 digital supply current 3 for core 5 10 15 ma i dd supply current for high-speed serial i/o and pvt 15 20 30 ma i dda1 analog supply current 1 for serializer 15 20 31 ma i dda2 analog supply current 2 for serializer 7 10 15 ma receiver ui unit interval 399.88 400 400.12 ps v rx_diffp-p differential input peak-to-peak voltage 0.205 - 1.2 v t rx_max_jitter maximum receiver jitter time - - 0.6 ui v idle_det_diffp-p electrical idle detect threshold 65 - 205 mv z rx_dc dc input impedance 40 50 60 ? z rx_high_imp_dc powered-down dc input impedance 200 - - k ? rl rx_diff differential return loss 15 - - db rl rx_cm common mode return loss 6 - - db t lock(cdr)(ref) cdr lock time (reference loop) - - 50 ? s t lock(cdr)(data) cdr lock time (data loop) - - 2.5 ? s t rx_latency receiver latency 1 clock cycle is 4 ns 6 - 13 clock cycle reference clock f clk(ref) reference clock frequency 99.97 100 100.03 mhz ? f mod(clk)(ref) reference clock modulation frequency range ? 0.5 - +0 % f mod(clk)(ref) reference clock modulation frequency 30 - 33 khz v ih(se)refclk refclk single-end high-level input voltage - 0.7 1.15 v v il(se)refclk refclk single-end low-level input voltage ? 0.3 0 - v z c-dc clock source dc impedance 40 50 60 ?
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 21 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy dv/dt rate of change of voltage at rising edge; measured from ? 150 mv to +150 mv on the differential waveform; figure 17 0.6 - 4.0 v/ns at falling edge; measured from +150 mv to ? 150 mv on the differential waveform; figure 17 0.6 - 4.0 v/ns v ih differential input high voltage +150 - - mv v il differential input low voltage - - ? 150 mv ? refclk duty cycle on pin refclk on pin refclk_n and pin refclk_p 40 - 60 % transmitter ui unit interval 399.88 400 400.12 ps v tx_diffp-p differential peak-to-peak output voltage 0.8 - 1.2 v t tx_eye_m-mjitter maximum time between the jitter median and maximum deviation from the median -3550ps t tx_jitter_max maximum transmitter jitter time - 60 100 ps v tx_de_ratio de-emphasized differential output voltage ratio ? 3.0 - ? 4.0 db t tx_rise d+/d ? tx output rise time 50 75 - ps t tx_fall d+/d ? tx output fall time 50 75 - ps v tx_cm_acp rms ac peak common mode output voltage --20mv ? v cm_dc_act_idle absolute delta of dc common mode voltage during l0 and electrical idle 0- 100mv ? v cm_dc_line absolute delta of dc common mode voltage between d+ and d ? 0- 25mv v tx_cm_dc tx dc common mode voltage 0 - 3.6 v i tx_short tx short-circuit current limit - 20 90 ma rl tx_diff differential return loss 12 - - db rl tx_cm common mode return loss 6 - - db z tx_dc transmitter dc impedance 40 50 60 ? c tx ac coupling capacitor 75 100 200 nf t lock(pll) pll lock time - - 50 ? s t tx_latency transmitter latency 1 clock cycle is 4 ns 4 - 9 clock cycle t p0s_exit_latency p0s state exit latency - - 2.5 ? s t p1_exit_latency p1 state exit latency - - 64 ? s t reset-phystatus reset_n high to phystatus low time --64 ? s table 18. pci express phy characteristics ?continued symbol parameter conditions min typ max unit
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 22 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy [1] reference voltage for sstl_2 class i i/o. fig 17. differential measurement points dv/dt at rising edge dv/dt at falling edge 002aad694 v ih = +150 mv 0.0 v v il = ?150 mv refclk+ minus refclk? table 19. pxpipe characteristics symbol parameter conditions min typ max unit f rxclk rxclk frequency 249.925 250 250.075 mhz f txclk txclk frequency 249.925 250 250.075 mhz v vrefs voltage on pin vrefs [1] 1.13 1.25 1.38 v v oh(sstl2) sstl_2 high-level output voltage ac v tt +0.61 - - v v ol(sstl2) sstl_2 low-level output voltage ac - - v tt ? 0.61 v v ih(sstl2) sstl_2 high-level input voltage ac v ref +0.31 - - v v il(sstl2) sstl_2 low-level input voltage ac - - v ref ? 0.31 v input signals; measured with respect to txclk t su(tx)(pxpipe) set-up time of pxpipe input signal see figure 18 500 - - ps t h(tx)(pxpipe) hold time of pxpipe input signal see figure 18 500 - - ps output signals; measured with respect to rxclk t su(rx)(pxpipe) set-up time of pxpipe output signal see figure 18 1500 - - ps t h(rx)(pxpipe) hold time of pxpipe output signal see figure 18 1500 - - ps fig 18. definition of pxpipe timing pxpipe input txclk pxpipe output rxclk t h(rx)(pxpipe) t su(rx)(pxpipe) t h(tx)(pxpipe) t su(tx)(pxpipe) 002aac316
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 23 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy t amb = 25 ? c; nominal v dd fig 19. transition eye t amb = 25 ? c; nominal v dd fig 20. non transition eye ?0.2 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 ? 0.1 0 differential signal (v) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 unit intervals 1.1 1.2 001aac789 ?0.2 ?0.6 ?0.5 ?0.4 ?0.3 ?0.2 ?0.1 0 0.1 0.2 0.3 0.4 0.5 0.6 ? 0.1 0 differential signal (v) 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1.0 unit intervals 1.1 1.2 001aac790
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 24 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 12. package outline fig 21. package outline sot643-1 (lfbga81) ball a1 index area 0.8 a 1 ba 2 unit d y e references outline version european projection issue date 00-11-01 02-03-28 iec jedec jeita mm 1.6 0.4 0.3 1.20 0.95 9.1 8.9 y 1 9.1 8.9 0.5 0.4 0.12 0.1 e 1 6.4 e 2 6.4 dimensions (mm are the original dimensions) sot643-1 mo-205 - - - e 0.15 v 0.08 w 0 5 10 mm scale sot643-1 lfbga81: plastic low profile fine-pitch ball grid array package; 81 balls; body 9 x 9 x 1.05 mm a max. a a 2 a 1 detail x y y 1 c x d e c a b c d e f h g j 246 9 8 1357 b a ball a1 index area e e e 1 b e 2 ac c b ? v m ? w m
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 25 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 13. soldering of smd packages this text provides a very brief insight into a complex technology. a more in-depth account of soldering ics can be found in application note an10365 ?surface mount reflow soldering description? . 13.1 introduction to soldering soldering is one of the most common methods through which packages are attached to printed circuit boards (pcbs), to form electr ical circuits. the soldered joint provides both the mechanical and the electrical connection. th ere is no single sold ering method that is ideal for all ic packages. wave soldering is often preferred when through-hole and surface mount devices (smds) are mixed on one printed wiring board; however, it is not suitable for fine pitch smds. reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization. 13.2 wave and reflow soldering wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. the wave soldering process is suitable for the following: ? through-hole components ? leaded or leadless smds, which are glued to the surface of the printed circuit board not all smds can be wave soldered. packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. also, leaded smds with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased pr obability of bridging. the reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. leaded packages, packages with solder balls, and leadless packages are all reflow solderable. key characteristics in both wave and reflow soldering are: ? board specifications, in cluding the board finish , solder masks and vias ? package footprints, including solder thieves and orientation ? the moisture sensitivit y level of the packages ? package placement ? inspection and repair ? lead-free soldering versus snpb soldering 13.3 wave soldering key characteristics in wave soldering are: ? process issues, such as application of adhe sive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave ? solder bath specifications, including temperature and impurities
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 26 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 13.4 reflow soldering key characteristics in reflow soldering are: ? lead-free versus snpb solderi ng; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see figure 22 ) than a snpb process, thus reducing the process window ? solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board ? reflow temperature profile; this profile includ es preheat, reflow (in which the board is heated to the peak temperature) and cooling down. it is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). in addition, the peak temperature must be low enough that the packages and/or boards are not damaged. the peak temperature of the package depends on package thickness and volume and is classified in accordance with ta b l e 2 0 and 21 moisture sensitivity precautions, as indicat ed on the packing, must be respected at all times. studies have shown that small packages reach higher temperatures during reflow soldering, see figure 22 . table 20. snpb eutectic process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 ? 350 < 2.5 235 220 ? 2.5 220 220 table 21. lead-free process (from j-std-020c) package thickness (mm) package reflow temperature ( ?c) volume (mm 3 ) < 350 350 to 2000 > 2000 < 1.6 260 260 260 1.6 to 2.5 260 250 245 > 2.5 250 245 245
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 27 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy for further information on temperature profiles, refer to application note an10365 ?surface mount reflow soldering description? . 14. appendix 14.1 errata added 2009-09-01 the px1011b (types px1011b-el1/g, PX1011BI-EL1/g, px1011b-el1/n and px1011b-el1/q900) is reported to sporadically produce communication failures in intel dx58s0-based systems in which the pcie transmitter has full active power state management (aspm) capability, and partic ularly when l0s m ode is supported. when the pcie transmitter goes idle (enters l0s) for the purpose of power saving and then returns to normal mode (exits l0s and enters l0), the px1011b receiver pll may randomly fail to lock, preventing it from properly interpreting the data being transmitted on the link. as a result the px1011b may send symbols to the link device that it cannot recognize. this is a l0s exit failure which may prevent the system from recovering and could cause the pcie protocol to eventually fail and the link to go down. if this occurs, the px1011b stays in the exit failure state indefinitely. the re ceiver can only be re-initiated by applying a hard reset to the phy, returning it to normal mode. you are strongly advised to disable the l0s mode whenever the px1011b is used. msl: moisture sensitivity level fig 22. temperature profiles for large and small components 001aac844 temperature time minimum peak temperature = minimum soldering temperature maximum peak temperature = msl limit, damage level peak temperature
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 28 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 15. abbreviations 16. references [1] pci express base specification ? rev. 1.0a - pcisig [2] phy interface for the pci express architecture (pipe) specification version 1.00 ? intel corporation table 22. abbreviations acronym description ber bit error rate bist built-in self test cmos complementary metal-oxide semiconductor crc cyclic redundancy check emi electromagnet ic interference esd electrostatic discharge fpga field programmable gate array ltssm link training and status state machine mac media access control p2s parallel to serial pci peripheral component interconnect pcs physical coding sub-layer phy physical layer pll phase-locked loop pipe phy interface for the pci express pvt process voltage temperature s2p serial to parallel serdes serializer and de-serializer skp skip sstl_2 stub series terminated logic for 2.5 volts
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 29 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 17. revision history table 23. revision history document id release date data sheet status change notice supersedes px1011b v.6 20110627 product data sheet - px1011b v.5 modifications: ? section 1 ? general description ? , third paragraph: added last sentence px1011b v.5 20110418 product data sheet - px1011b v.4 modifications: ? table 2 ?ordering information?: ? added type number px1011b-el1/q900 ? added table note [1] and cross-reference at px1011b-el1/q900 ? table 4 ?lead-free package marking?: added marking px1011b-el1/q ? figure 2 ?pin configuration for lfbg a81?: added type number px1011b-el1/q900 ? table 18 ?pci express phy characteristics?: ? sub-section ?supplies?, i dd , supply current: max value changed from ?28 ma? to ?30 ma? ? sub-section ?supplies?, i dda1 , analog supply current 1: max value changed from ?28 ma? to ?31 ma? ? sub-section ?receiver?, v rx_diffp-p , differential input peak-to-peak voltage: min value changed from ?0.175 v? to ?0.205 v? ? sub-section ?receiver?, v idle_det_diffp-p , electrical idle detect threshold: max value changed from ?175 mv? to ?205 mv? ? section 14.1 ?errata added 2009-09-01?: added type number px1011b-el1/q900 to first sentence px1011b v.4 20090904 product data sheet - px1011b v.3 modifications: ? section 14: errata information added px1011b v.3 20081020 product data sheet - px1011b v.2 modifications: ? added type number px1011b-el1/n (affects section 2.6 ?miscellaneous?, table 2 ?ordering information?, (new) table 3 ?leaded package marking?, figure 2 ?pin configuration for lfbga81?) px1011b v.2 20080319 product data sheet - px1011b v.1 px1011b v.1 20080213 objective data sheet - -
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 30 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy 18. legal information 18.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 18.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? the information and data provided in a product data sheet shall define the specification of the product as agreed between nxp semiconductors and its customer , unless nxp semiconductors and customer have explicitly agreed otherwis e in writing. in no event however, shall an agreement be valid in which the nxp semiconductors product is deemed to offer functions and qualities beyond those described in the product data sheet. 18.3 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? 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applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconductors products, and nxp semiconductors accepts no liability for any assistance with applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. limiting values ? stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. quick reference data ? the quick reference data is an extract of the product data given in the limiting values and characteristics sections of this document, and as such is not comp lete, exhaustive or legally binding. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
px1011b all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. product data sheet rev. 6 ? 27 june 2011 31 of 32 nxp semiconductors px1011b pci express stand-alone x1 phy export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from national authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. 18.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 19. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors px1011b pci express stand-alone x1 phy ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 27 june 2011 document identifier: px1011b please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 20. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 2.1 pci express interface . . . . . . . . . . . . . . . . . . . . 1 2.2 phy/mac interface . . . . . . . . . . . . . . . . . . . . . 1 2.3 jtag interface . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 power management . . . . . . . . . . . . . . . . . . . . . 2 2.5 clock. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 2.6 miscellaneous . . . . . . . . . . . . . . . . . . . . . . . . . . 2 3 quick reference data . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 marking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 6 block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 8 functional description . . . . . . . . . . . . . . . . . . . 8 8.1 receiving data . . . . . . . . . . . . . . . . . . . . . . . . . 8 8.2 transmitting data . . . . . . . . . . . . . . . . . . . . . . . 9 8.3 clocking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.4 reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 8.5 power management . . . . . . . . . . . . . . . . . . . . 10 8.6 receiver detect. . . . . . . . . . . . . . . . . . . . . . . . 11 8.7 loopback . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 8.8 electrical idle . . . . . . . . . . . . . . . . . . . . . . . . . 13 8.9 clock tolerance compensati on . . . . . . . . . . . . 14 8.10 error detection . . . . . . . . . . . . . . . . . . . . . . . . 15 8.10.1 8b/10b decode errors . . . . . . . . . . . . . . . . . . . 16 8.10.2 disparity errors . . . . . . . . . . . . . . . . . . . . . . . . 16 8.10.3 elastic buffer . . . . . . . . . . . . . . . . . . . . . . . . . . 16 8.11 polarity inversion . . . . . . . . . . . . . . . . . . . . . . 17 8.12 setting negative disparity . . . . . . . . . . . . . . . . 18 8.13 jtag boundary scan interface . . . . . . . . . . . . 18 9 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . 19 10 thermal characteristics . . . . . . . . . . . . . . . . . 19 11 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 20 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 24 13 soldering of smd packages . . . . . . . . . . . . . . 25 13.1 introduction to soldering . . . . . . . . . . . . . . . . . 25 13.2 wave and reflow soldering . . . . . . . . . . . . . . . 25 13.3 wave soldering . . . . . . . . . . . . . . . . . . . . . . . . 25 13.4 reflow soldering . . . . . . . . . . . . . . . . . . . . . . . 26 14 appendix . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 14.1 errata added 2009-09-01 . . . . . . . . . . . . . . . . 27 15 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 28 16 references . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 17 revision history . . . . . . . . . . . . . . . . . . . . . . . 29 18 legal information . . . . . . . . . . . . . . . . . . . . . . 30 18.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 30 18.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . 30 18.4 trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . 31 19 contact information . . . . . . . . . . . . . . . . . . . . 31 20 contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32

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